Blue Cheetah Collaborates with LG to Demonstrate Successful Silicon Bring-Up of Chiplet-Based Design

Blue Cheetah Analog Design and LG Electronics Inc. (LG) announced that they are collaborating and have demonstrated silicon success for a new generation of chiplets that can potentially be used in LG’s future AI-enabled products. The successful silicon bring-up of a complex System-in-Package (SiP), including chiplets with processors, DDR memory interfaces, AI accelerators, and Blue Cheetah’s die-to-die (D2D) interconnect, marks a significant milestone in the partnership.

LG, a global leader in innovative consumer electronics and home appliances, used Blue Cheetah’s BlueLynx D2D interconnect IP for its multi-chiplet design. Blue Cheetah provides its state-of-the-art IP solutions in 16nm, 12nm, 7nm, 6nm, 5nm, 4nm, and below across multiple semiconductor foundries. The IP supports versatile packaging options, including standard and advanced, supporting multiple bump pitches, metal stacks, and orientations. The physical (PHY) IP solutions integrate with on-die buses using popular standards like AMBA CHI, AXI, and ACE.

“We chose Blue Cheetah because the company offers the fastest, lowest-risk path to customized chiplet interconnect solutions that we can potentially use across product lines,” said Kim Jin-Gyeong, SVP and Head of SoC R&D Center of LG. “The company’s BlueLynx die-to-die interconnect IP allows us to combine chiplets in varying process technologies, facilitating more cost-effective scaling and greater IP reuse.”

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“We are excited to be working with LG, one of the largest TV manufacturers and a leader in home appliance, air solutions, and home entertainment,” said Elad Alon, CEO at Blue Cheetah. “Successful silicon bring-up of a complex SiP is an essential first step. We look forward to a productive alliance creating innovative chiplet solutions with LG.”

Blue Cheetah‘s BlueLynx D2D interconnect subsystem IP provides customizable physical (PHY) and link layer chiplet interfaces and can support the Universal Chiplet Interconnect Express (UCIe) and Open Compute Project (OCP) Bunch of Wires (BoW) standards.

SOURCE: PRNewsWire