IBM and Siemens have entered into a strategic research alliance aimed at driving the development and scalable manufacturing of IBM’s proprietary nanostack architecture. The joint initiative combines IBM’s semiconductor device innovation with Siemens’ advanced electronic design automation (EDA), process simulation, lithography optimization, and industrial manufacturing software suite.
Unveiled earlier this year, nanostack represents a fundamental departure from conventional planar chip designs. By staggering and vertically stacking 3D nanosheet-based transistors, the architecture enables density levels of nearly 100 billion transistors within a footprint no larger than a fingernail at the 7-angstrom node. Crucially, this multi-layered framework allows engineers to integrate distinct material compositions across individual stacked layers, providing independent optimization of performance and energy consumption per transistor while accelerating SRAM scaling.
Having successfully validated the physical viability of the nanostack framework, IBM is focusing the next phase of development on resolving the engineering and lithographic hurdles required for commercial volume production.
Under the terms of the agreement, IBM and Siemens will collaborate on advanced design methodologies, computational lithography, and simulation frameworks targeting nodes beyond the 7-angstrom mark. Central to the joint research is the creation of high-fidelity virtual digital twins of the nanostack architecture. These predictive models will allow engineers to simulate device physics, refine layout parameters, and preemptively resolve fabrication bottlenecks prior to physical wafer processing.
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“Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D, representing a new paradigm for the semiconductor industry and a path forward for the logic scaling needed to support AI and other emerging technologies over the coming decade,” said Huiming Bu, Vice President of Silicon Technology R&D, IBM. “We are thrilled to work with Siemens as we continue to advance this technology and explore new approaches to extend angstrom-level scaling with nanostack.”
“Scaling semiconductors into the angstrom era demands tightly coupled co-optimization between device physics, EDA design and manufacturing software, and manufacturing. As physical AI places extraordinary demands on silicon architecture, IBM’s 3D nanostack design represents a pivotal leap forward,” said Ankur Gupta, Executive Vice President, EDA IC Portfolio, Siemens. “Siemens’ collaboration with IBM to advance virtual modeling, simulation, lithography, and design software optimizations needed to address physical limitations early and accelerate the development of these complex architectures is truly pioneering.”
By pairing hardware R&D with advanced EDA and computational simulation, both organizations aim to shorten innovation cycles and establish a repeatable industrial foundation to bring 3D nanostack technology from the research laboratory to mass market foundry deployment.